NAME

       vhier - Return all files in a verilog hierarchy using Verilog::Netlist

SYNOPSIS

         vhier --help
         vhier [verilog_options] [-o filename] [verilog_files.v...]

DESCRIPTION

       Vhier reads the Verilog files passed on the command line and outputs a tree of all of the filenames,
       modules, and cells referenced by that file.

VERILOG ARGUMENTS

       The following arguments are compatible with GCC, VCS and most Verilog programs.

       +define+var+value =item -Dvar=value
           Defines the given preprocessor symbol.

       -F file
           Read  the  specified file, and act as if all text inside it was specified as command line parameters.
           Any relative paths are relative to the directory containing the specified file.

       -f file
           Read the specified file, and act as if all text inside it was specified as command  line  parameters.
           Any relative paths are relative to the current directory.

       +incdir+dir =item -Idir
           Add  the  directory  to  the  list  of directories that should be searched for include directories or
           libraries.

       +libext+ext+ext...
           Specify the extensions that should be  used  for  finding  modules.   If  for  example  module  x  is
           referenced, look in x.ext.

       -sv Specifies  SystemVerilog  language  features should be enabled; equivalent to "--language 1800-2023".
           This option is selected by default, it exists for compatibility with other simulators.

       -y dir
           Add the directory to the list of directories that should  be  searched  for  include  directories  or
           libraries.

VHIER ARGUMENTS

       --help
           Displays this message and program version and exits.

       --o file
           Use the given filename for output instead of stdout.

       --cells
           Show the module name of all cells in top-down order.

       --forest
           Show "ASCII-art" hierarchy tree of all cells (like ps --forest)

       --input-files
           Show  all  input  filenames.   Copying all of these files should result in only those files needed to
           represent the entire design.

       --includes
           Show each source filename that includes another filename.  The included filename will be as specified
           in the original source filename, so it may be necessary to resolve  it  into  an  absolute  path  for
           further processing.

       --instance
           With --cells or --forest, show module instance names.

       --language <1364-1995|1364-2001|1364-2005|1800-2005|1800-2009|1800-2012|1800-2017|1800-2023>
           Set  the  language standard for the files.  This determines which tokens are signals versus keywords,
           such as the ever-common "do" (data-out signal, versus a do-while loop keyword).

       --resolve-files
           Show resolved filenames passed on the command line.  This  will  convert  raw  module  and  filenames
           without  paths  to  include  the library search path directory.  Output filenames will be in the same
           order as passed on the command line.   Unlike  --input-files  or  --module-files,  hierarchy  is  not
           traversed.

       --module-files
           Show all module filenames in top-down order.  Child modules will always appear as low as possible, so
           that reversing the list will allow bottom-up processing of modules.  Unlike input-files, header files
           are not included.

       --modules
           Show all module names.

       --no-missing
           Do not complain about references to missing modules.

       --missing-modules
           With --nomissing, show all modules that are not found.

       --skiplist file
           Given  file  contains  a  list  of  regular expressions, one per line. If a module name in the design
           hierarchy matches one of these expressions, skip showing that module and any sub-hierarchy.

       --synthesis
           Define SYNTHESIS, and ignore text between "ambit", "pragma", "synopsys" or "synthesis"  translate_off
           and  translate_on  meta comments.  Note using metacomments is discouraged as they have led to silicon
           bugs (versus ifdef SYNTHESIS); see <https://www.veripool.org/papers/TenIPEdits_SNUGBos07_paper.pdf>.

       --top-module module
           Start the report at the specified module name, ignoring all modules that are not  the  one  specified
           with  --top-module  or  below,  and  report  an  error  if the --top-module specified does not exist.
           Without this option vhier will report all modules, starting at the module(s) that  have  no  children
           below them.

           Note  this  option will not change the result of the --input-files list, as the files needed to parse
           any design are independent of which modules are used.

       --version
           Displays program version and exits.

       --xml
           Create output in XML format.

DISTRIBUTION

       Verilog-Perl is part of the <https://www.veripool.org/> free Verilog EDA software tool suite.  The latest
       version is available from CPAN and from <https://www.veripool.org/verilog-perl>.

       Copyright 2005-2024 by Wilson Snyder.  This package is free software;  you  can  redistribute  it  and/or
       modify  it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic
       License Version 2.0.

AUTHORS

       Wilson Snyder <wsnyder@wsnyder.org>

SEE ALSO

       Verilog-Perl, Verilog::Getopt, Verilog::Preproc, Verilog::Netlist

perl v5.38.2                                       2024-03-31                                          VHIER(1p)